Recent Posts

Weekly Tech Roundup – 27 September 2026

The week ending 27 September 2026 brought several important developments across power electronics, embedded control and semiconductor technology.

For power-electronics engineers, the most relevant announcement is Infineon’s new PSoC Control C3 Performance Line, which combines high-speed real-time control, high-resolution PWM, hardware acceleration and post-quantum security for applications including AI server power supplies, solar inverters, SMPS, EV charging and motor control.

Another major development came from DG Matrix and STMicroelectronics, where next-generation SiC technology has enabled a 400 kW solid-state transformer platform in essentially the same power-module footprint previously used for 200 kW.

Renesas also expanded its GreenPAK family with the extremely compact SLG46801 configurable mixed-signal IC, while Cadence introduced an AI agent for specification-to-RTL generation and early power-performance-area optimization.

In India, Tata Electronics announced seven semiconductor-industry partnerships covering wafer fabrication, assembly and testing, advanced packaging and semiconductor materials, further expanding the domestic semiconductor ecosystem.




1. Infineon Launches PSoC Control C3 Performance Line for Digital Power Control

Company: Infineon Technologies
Family: PSoC Control C3 Performance Line
Announcement: 22 September 2026

Infineon introduced the PSoC Control C3 Performance Line, a new family of microcontrollers specifically designed for high-performance real-time control applications.

The family is based on Arm Cortex-M33 architecture and is aimed at applications including AI server power supplies, AC-DC and DC-DC converters, Solar inverters, EV charging, Industrial SMPS, Motor control, Robotics, Drones and Telecommunications power systems.

The devices provide up to 180 MHz Cortex-M33 operation, while some configurations use dual Cortex-M33 cores with hardware acceleration. The family provides up to 512 KB Flash and 240 KB SRAM with ECC. One of the most interesting features for power-electronics designers is the Programmable Power Control Accelerator (PPCA). The devices also provide High-resolution PWM, Up to 25 MSPS analog capability, Custom Logic Block, Event Processing Unit, 3p3z digital filters, Fast analog and digital peripherals, Hardware acceleration, Secure boot, Firmware protection and Post-Quantum Cryptography support. Infineon specifies PWM resolution below 100 ps on applicable devices, which is particularly relevant for high-frequency switching converters.

Why This Is Important for Power Electronics

Traditional MCU-based digital power control requires the CPU to execute ADC acquisition, control-law calculations, PWM updates and protection handling. As switching frequency increases, the available control-cycle time becomes very small.

At such frequencies, software execution time, ADC latency, interrupt latency and PWM update timing become critical. A hardware accelerator can move portions of the control loop away from the CPU and make timing more deterministic.

Engineer’s Perspective

This development is particularly relevant to designers moving from analog PFC/LLC controllers toward fully digital power control.

A modern digital power controller may need to perform:

ADC sampling → filtering → compensator → protection → PWM update

within a fraction of one switching cycle.

The combination of hardware accelerators, high-resolution PWM and fast analog peripherals can therefore allow the same MCU to control higher-frequency GaN and SiC converters. The addition of post-quantum security is also significant for connected industrial and infrastructure equipment because the controller is increasingly part of a networked system rather than simply a local PWM generator.


2. DG Matrix Doubles Solid-State Transformer Power to 400 kW Using ST SiC Technology

Companies: DG Matrix and STMicroelectronics
Platform: Interport multi-port solid-state transformer
Power: 400 kW
Efficiency: Above 98.5%
Announcement: 24–25 September 2026

DG Matrix announced that its Interport solid-state transformer platform has reached 400 kW, compared with the previous 200 kW capability, while maintaining essentially the same power-module footprint. The system uses STMicroelectronics’ latest-generation silicon-carbide technology. The platform is designed for high-density power conversion and can be applied to AI data centers, 800 VDC power architectures, Utility microgrids, Electrification infrastructure and Solid-state transformer applications.

DG Matrix reports efficiency above 98.5%. The company attributes the increased power density to the use of advanced ST SiC devices combined with a thermally optimized package.

Why SiC Is Important Here

At hundreds of kilowatts, conduction and switching losses become major thermal-design constraints. Therefore, the overall improvement comes from the combination of Lower semiconductor losses, Higher switching capability, Better thermal resistance, Reduced parasitic inductance, Improved magnetic utilization and Optimized converter topology.

Engineer’s Perspective

The interesting part of this announcement is not simply the 400 kW number. The real engineering achievement is increasing power capability without proportionally increasing the physical power-module footprint. That is exactly the challenge facing AI data centers. As rack power increases, engineers cannot simply make every converter twice as large. The result would be unacceptable increases in Cooling requirements, Busbar size, Floor-space requirements, Converter volume and Installation complexity.

Wide-bandgap devices such as SiC therefore become an important enabler of higher power density.


3. Renesas Introduces Ultra-Compact SLG46801 GreenPAK Mixed-Signal IC

Company: Renesas Electronics
Part: SLG46801
Package: 1.155 mm × 1.155 mm WLCSP option
Announcement: 24 September 2026

Renesas expanded its GreenPAK configurable mixed-signal IC family with the SLG46801. The device combines analog, digital and timing functions into a very small programmable IC. Renesas also offers a 12-pin STQFN package.

The SLG46801 includes:

·         Two high-speed analog comparators

·         Configurable lookup tables

·         D-type flip-flops/latches

·         Delay and counter functions

·         10 kHz oscillator

·         25 MHz oscillator

·         I²C interface

·         Voltage-tolerant GPIO

·         Power-on reset

·         Multi-time-programmable memory

The operating/programming voltage range is 1.71 V to 5.5 V.

What Is Multi-Time Programmability?

Traditional programmable logic devices may be one-time programmable. The SLG46801 uses MTP — Multi-Time Programmable memory. This allows the configuration to be changed multiple times after the hardware has been designed.

That means an engineer can modify Logic functions, Timing, Threshold-related behavior, Sequencing and Control functions without replacing the PCB.

Engineer’s Perspective

GreenPAK devices are particularly interesting for small control boards where using a complete MCU would be excessive.For example, instead of using:

MCU + comparator + timer + logic gates + delay circuit

a designer may implement several of those functions inside a single GreenPAK.

This can be useful in Power sequencing, Battery protection, Small motor controllers, Sensor interfaces, Fault detection, Reset generation and Power-supply housekeeping.

For an engineer designing multiple hardware revisions, MTP capability can also reduce development risk because the logic can be modified without redesigning the entire PCB.


4. Cadence Introduces AI Agent for Automated RTL Generation and PPA Optimization

Company: Cadence Design Systems
Technology: ChipStack AI Super Agent – RTL Generation Agent
Announcement: 22 September 2026

Cadence announced a new AI agent that can generate and refine RTL from high-level specifications while simultaneously considering power, performance and area (PPA).

The technology extends Cadence’s ChipStack AI Super Agent platform from verification and debug toward actual RTL generation and optimization. According to Cadence’s early evaluations, the RTL Generation Agent achieved:

·         24% average area reduction

·         18% average power reduction

·         100% functional accuracy

when compared with pure foundation-model code generation in the company’s early trials. These figures are Cadence-reported evaluation results rather than independent benchmark results. Honda R&D is evaluating the technology for automotive SoC development.

Why This Matters to Electronics Engineers

The semiconductor design flow traditionally looks approximately like:

Specification → Architecture → RTL → Simulation → Synthesis → PPA analysis → Optimization → Verification

AI-assisted RTL generation attempts to automate portions of this cycle.

Instead of an engineer manually writing every RTL block, the engineer can provide higher-level requirements and allow the AI agent to generate and refine RTL.

The important point is that this is not simply “AI writing Verilog.”

The tool connects the AI agent to established EDA technologies so that generated RTL can be analyzed for Functional correctness, Area, Timing, Power and Implementation constraints.

Engineer’s Perspective

This could eventually change how engineers approach custom digital control hardware.

For power-electronics designers, this is particularly interesting because many advanced digital power systems contain custom hardware functions such as PWM engines, Protection logic, ADC synchronization, Hardware state machines, Current-limit logic, Dead-time generation, Fault interlocks and Digital filters.

Some of these functions currently require dedicated FPGA or ASIC development.

AI-assisted RTL generation could reduce the barrier to creating customized hardware accelerators. Cadence says the expanded capabilities are expected to reach select early-access customers in Q4 2026.


5. Tata Electronics Signs Seven Agreements to Expand India’s Semiconductor Value Chain

Company: Tata Electronics
Event: SEMICON India 2026
Announcement: 24 September 2026

Following SEMICON India 2026, Tata Electronics announced a set of seven collaborations intended to strengthen different parts of India’s semiconductor ecosystem.

The agreements cover areas including:

·         Wafer fabrication

·         Assembly and testing

·         Advanced semiconductor packaging

·         Semiconductor materials

·         Supply-chain localization

·         Technology development

·         Talent development

One important collaboration is with Nexperia, covering front-end wafer fabrication as well as back-end assembly and testing and broader ecosystem development. Tata Electronics plans to manufacture/package relevant semiconductor products through facilities in Dholera, Gujarat and Jagiroad, Assam.

A separate collaboration with Fujifilm is focused on semiconductor materials for the Dholera fab. Fujifilm is reported to plan an investment of approximately ₹800 crore for a semiconductor-materials plant in Dholera.

Other collaborations involve semiconductor packaging materials and technology.

Why This Matters for Electronics Designers

A semiconductor ecosystem is much more than a wafer fabrication plant.

A complete ecosystem requires:

Design → EDA → Wafer fabrication → Packaging → Testing → Materials → Equipment → Distribution → System manufacturing

Weakness at any one of these stages can increase cost or create supply-chain dependence.

For Indian electronics manufacturers, development of local fabrication, packaging and materials capabilities could eventually provide greater access to domestically manufactured semiconductor components.

Engineer’s Perspective

For power-electronics engineers, the long-term significance is particularly interesting.

India has a large and growing market for:

·         EV chargers

·         Solar inverters

·         UPS systems

·         Industrial drives

·         BLDC motor controllers

·         Battery-management systems

·         Telecom power supplies

·         Consumer power supplies

These applications require large volumes of MOSFETs, IGBTs, SiC devices, gate drivers, controllers, analog ICs and sensors.

A stronger domestic semiconductor ecosystem could therefore eventually connect directly with India’s power-electronics manufacturing industry.


6. India Continues to Build the Semiconductor-to-System Manufacturing Chain

The semiconductor announcements this week also show that India’s focus is gradually moving beyond simply attracting semiconductor fabs.

SEMICON India 2026 highlighted activity across:

·         Wafer manufacturing

·         OSAT

·         Advanced packaging

·         Semiconductor materials

·         Semiconductor equipment

·         Chip design

·         Electronics manufacturing

Tata Electronics’ collaborations are particularly relevant because they address several of these layers simultaneously.

This is important for electronics engineers because semiconductor availability alone does not create a complete electronics industry.

The ability to manufacture the complete product requires semiconductor suppliers, PCB manufacturers, magnetics suppliers, EMS companies, test facilities, mechanical suppliers and system integrators to develop together.

For India’s power-electronics industry, that could eventually create more opportunities for locally designed and manufactured:

·         EV chargers

·         Solar power converters

·         Energy-storage systems

·         Motor drives

·         Industrial SMPS

·         Power modules

·         Control boards


Engineer’s Weekly Takeaway

The strongest theme of this week’s developments is increasing integration between semiconductor devices, digital control and the complete power-conversion system.

Three developments stand out from an engineering perspective.

1. Digital power control is becoming more specialized

Infineon’s PSoC Control C3 shows that the digital controller itself is increasingly being optimized specifically for power conversion.

High-resolution PWM, hardware control accelerators and fast analog peripherals are becoming as important as CPU clock speed.

2. SiC is enabling much higher system power density

The DG Matrix example demonstrates the system-level effect of SiC.

Moving from 200 kW to 400 kW without proportionally increasing module footprint shows how wide-bandgap semiconductor technology can change the architecture of high-power converters.

3. More functionality is moving into programmable hardware

Renesas GreenPAK takes the approach down to very small mixed-signal control functions, while Cadence is moving AI into the RTL design process.

The common direction is:

More functionality → fewer discrete components → smaller hardware → more programmable systems

For power-electronics designers, this means future converters are likely to contain much more intelligence inside the power stage itself.

Instead of thinking of a converter as:

MOSFET + diode + controller + passive components

the emerging architecture is closer to:

Power semiconductor + gate driver + sensing + digital control + protection + communication + security

all designed as one integrated system.

No comments